FIG. 10(a) shows a peripheral circuit within a memory array of a conventional semiconductor memory. Within the peripheral circuit, a sense amplifier is connected to a pair of bit lines BL and/BL to which a dynamic-type memory cell, not shown, is connected. The sense amplifier includes N-channel MOS transistors Q1 and Q2 connected in series between bit lines BL and/BL, with the drain and gate of each transistor connected to a different bit line and with the sources of the transistors connected in common to a sense amplifier drive signal line/SAN. A column select circuit is constituted by N-channel MOS transistors Q3 and Q4. MOS transistor Q3 is connected between the bit line BL and a data line DQ, and MOS transistor Q4 is connected between the bit line/BL and a data line/DQ, respectively. The gates of the MOS column select transistors are commonly connected to a column select line CSL.
The FIG. 10(a) circuit operates as follows. When a word line, not shown, is activated and the memory cell is selected, a very small potential difference is generated between the pair of bit lines BL and/BL. Next, the potential of the sense amplifier drive line/SAN is changed from 1/2 V.sub.CC (corresponding to a voltage of approximately a half of an internal power source voltage) to V.sub.SS (ground potential). Consequently, the very small potential difference between BL and/BL is amplified by MOS transistors Q1 and Q2 and the potential of either one of BL and/BL falls to a potential of V.sub.SS. The amplified potential difference is transferred to the pair of data lines DQ and /DQ via the column select transistors Q3 and Q4 and then the potential difference is converted into a logic signal level by a data line amplifying circuit, not shown, so that the sensed potential difference is read out from the chip as an output data.
It has conventionally been difficult to sufficiently reduce the access time required for the circuit shown in FIG. 10(a) for the following reasons. Although only a single pair of bit lines are shown for simplicity in FIG. 10(a), actually several hundreds of pairs of bit lines are typically driven by the same sense amplifier drive line/SAN. Accordingly, it is difficult to drive the sense amplifier drive line/SAN at high speed even when MOS transistors having a high drive capacity are used to drive the line/SAN. The large capacitance of the sense amplifier drive line/SAN prevents the drive circuitry from quickly activating the sense amplifiers, has been one obstacle to speeding up conventional dynamic-type memory.
A peripheral circuit like that shown in FIG. 10(b) has been developed to attempt to address the above problem. The circuit of FIG. 10(a) is modified to provide the circuit of FIG. 10(b) by adding a MOS transistor Q5 connected between a common source terminal of the sense amplifier and the ground potential and a MOS transistor Q6 connected between the common source terminal and the sense amplifier drive line/SAN. The gate of MOS transistor Q5 is driven by the column select line CSL and the gate of MOS transistor Q6 is connected to the V.sub.CC (the internal power source potential).
Next, the operation of the FIG. 10(b) circuit is described. When a word line, not shown, is activated and the memory cell is selected, a very small potential difference arises between the pair of bit lines BL and/BL. Next, the potential of the sense amplifier drive line/SAN changes from 1/2 V.sub.CC (approximately one half of the internal power source voltage) to V.sub.SS (ground potential). As in the FIG. 10(a) circuit,/SAN does not change rapidly because of the large capacitance of the line driven by/SAN. Next, the potential of the column select line CSL changes from V.sub.SS to V.sub.CC for column selection whether or not/SAN has reached V.sub.SS. When CSL switches to V.sub.CC ("high"), the MOS transistor Q5 is driven to turn on, the node at the sources of the sense amplifier transistors Q1, Q2 falls to V.sub.SS, and the sense amplifier is driven at high speed. As a result, a very small potential difference is amplified at high speed by the operation of the MOS transistors Q1 and Q2 and one of the potentials of BL or/BL quickly falls to V.sub.SS. The amplified potential difference is transferred to the pair of data lines DQ and/DQ via the column transistors Q3 and Q4 and the amplified potential difference is converted into a logic level signal by a data line amplifying circuit, not shown, and the amplitude difference is read out from the chip as data. Sense amplifiers connected to pairs of bit lines other than the pair of bit lines selected by the column select line CSL are driven only by the sense amplifier drive lines/SAN in a manner similar to that of the FIG. 10(a) circuit so that the non-selected bit lines are driven at low speed compared with the selected pair of bit lines. According to the circuit shown in FIG. 10(b), it is possible to speed up operation without significantly increasing power consumption because only the sense amplifier corresponding to the selected column is activated at higher speed
It is difficult to use the circuit shown in FIG. 10(b) in a dynamic-type memory of the type shown in FIG. 3. In the illustrated memory, a number of memory cell arrays ("Cell") are arranged alternatively along the row direction. Row selection is performed by a common column decoder circuit C/D using a common column select line CSL. When the column select line CSL goes high to selected one memory cell at high speed in the FIG. 10(b) circuit, all the sense amplifiers connected to the same column select line CSL are activated. In addition, when the sense amplifier connected to the particular memory cell is activated, all the sense amplifiers belonging to the particular memory cell array Cell which includes the selected memory cell are activated. Thus, a cross-shaped group of sense amplifiers including one row and one column are simultaneously activated so that a high level of current consumption accompanies the activation of the selected sense amplifier. To implement the peripheral circuit of FIG. 10(b) in a memory such as the one shown in FIG. 3, then, it is necessary to arrange a column decode circuit C/D for each memory cell array Cell. This is because each of the common CSL must be driven independently to reduce access speed without increasing power consumption. Providing the large number of column decode circuits necessary to implement a circuit having the sufficient number of column decoders requires a substantial and undesirable increase in the chip area.